Embodiments of the present invention relate to a semiconductor memory device, and more particularly to a technology for reducing the size of circuitry relating to a bad block of a NAND flash memory device.
Semiconductor memory devices capable of storing data therein are generally classified into Random Access Memory (RAM) devices and Read Only Memory (ROM) devices.
Data stored in the RAM device is lost when power supply is stopped, so that the RAM device is referred to as a volatile memory device. On the other hand, data stored in the ROM device is not lost even when power supply is stopped. Thus, the ROM device is referred to as a non-volatile memory device.
A flash memory device serving as a non-volatile memory device is characterized in that writing and erasing of data are electrically performed. A memory cell array of the flash memory device is composed of a plurality of blocks, and each of the blocks is composed of a plurality of pages. A block is used as a minimum unit for erasing data stored in the memory cell array.
During a program or erase operation, the flash memory device may use not only a tunneling effect based on a high-energy barrier but also a hot carrier effect generated when hot carriers having high kinetic energy pass through an insulation material.
Defective or failed flash memory cells may occur because of a plurality of limitations encountered in a process for fabricating a highly-integrated flash memory device.
In the process for fabricating or operating the flash memory device, a fatal defect frequently occurs in a memory cell of the flash memory device. Assuming that a specific block includes at least one memory cell having a defect, the specific block is generally referred to as a bad block. If the number of bad blocks in the flash memory device is equal to or higher than a predetermined value, the flash memory device is determined to be defective.
On the other hand, if the number of bad blocks in the flash memory device is smaller than the predetermined value, the flash memory device can manage the bad blocks using a variety of methods. A representative method from among the various methods is a bad-block mapping method for replacing each bad block with a redundant block.
According to the bad-block mapping method, an address of each bad block is recognized, and data is prevented from being written in or read from the bad block. The bad block is replaced with a redundant block, and a write or read operation is performed through the redundant block when the address of the bad block is input.
If a NAND flash memory device has one or more bad bits, the NAND flash memory device determines a block having the one or more bad bits to be a bad block, and stores information regarding the bad block, e.g., an address of the bad block. After that, if an operation for accessing the bad block is performed, the bad block is identified by a corresponding address, so that the operation for accessing the bad block is blocked.
A conventional non-volatile memory device includes a comparator circuit per plane to determine whether an input address corresponds to a bad block.
Thus, as the number of planes increases, the chip size also increases. Particularly, as the non-volatile memory device is highly integrated, it becomes more important to reduce the chip size.